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integrated synthesizer and vco adf4360-8 rev. 0 in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . specifications subjec t to chan g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2004 analog de vices, i n c. al l r i ght s r e ser v ed . fea t ures output freq ue ncy range: 65 mhz to 40 0 mh z 3.0 v to 3.6 v p o wer supply 1.8 v logic compatibility integer-n synt hesizer programmable output power level 3-wire seri al in terface digital lock det e ct hardware and software power-down mode applic a t io ns system clock generation test eq uipmen t wireless lans catv equipment gener a l description the ad f4360-8 is a n in t e g r a t e d in teg e r - n sy n t h e sizer and v o l t a g e con t r o l l ed os cil l a t o r ( v co). th e ad f4 360-8 cen t er f r e q u e nc y i s s e t b y e x te r n a l i ndu c t or s . t h i s a l l o w s a f r e q u e nc y ra n g e o f betw een 65 mh z t o 40 0 mh z. c o n t ro l of a l l t h e on - c h i p re g i st e r s i s t h rou g h a s i m p l e 3 - w i re in t e r f ace . the de v i ce o p er a t es wi t h a p o w e r s u p p l y ra n g in g f r o m 3.0 v to 3.6 v and can b e p o w e r e d do w n w h e n n o t i n us e. func ti on a l bl ock di a g r a m muxout cp v vco ref in clk data le av dd dv dd ce agnd dgnd cpgnd r set v tune c c c n l2 l1 rf out a rf out b vco core phase comparator mute n = b charge pump output stage 13-bit b counter 14-bit r counter 24-bit function latch 24-bit data register multiplexer lock detect a d f436 0- 8 04763- 001 fi g u r e 1 .
adf4360-8 rev. 0 | page 2 of 24 table of contents specifications..................................................................................... 3 timing characteristics..................................................................... 5 absolute maximum ratings............................................................ 6 transistor count........................................................................... 6 esd caution.................................................................................. 6 pin configuration and function descriptions............................. 7 typical performance characteristics ............................................. 8 circuit description......................................................................... 10 reference input section............................................................. 10 n counter.................................................................................... 10 r counter .................................................................................... 10 pfd and charge pump.............................................................. 10 muxout and lock detect...................................................... 10 input shift register..................................................................... 11 vco ............................................................................................. 11 output stage................................................................................ 12 latch structure ........................................................................... 13 control latch .............................................................................. 17 n counter latch......................................................................... 18 r counter latch ......................................................................... 18 choosing the correct inductance value ................................. 19 fixed frequency lo................................................................... 19 power-up..................................................................................... 20 interfacing ................................................................................... 20 pcb design guidelines for chip scale package........................... 20 output matching ........................................................................ 21 outline dimensions ....................................................................... 22 ordering guide .......................................................................... 22 revision history 10/04revision 0: initial version
adf4360-8 rev. 0 | page 3 of 24 specifications 1 av dd = dv dd = v vco = 3.3 v 10%; agnd = dgnd = 0 v; t a = t min to t max , unless otherwise noted. table 1. parameter b version unit conditions/comments ref in characteristics ref in input frequency 10/250 mhz min/max for f < 10 mhz, use a dc-coupled cmos-compatible square wave, slew rate > 21 v/s. ref in input sensitivity 0.7/av dd v p-p min/max ac-coupled. 0 to av dd v max cmos-compatible. ref in input capacitance 5.0 pf max ref in input current 60 a max phase detector phase detector frequency 2 8 mhz max charge pump i cp sink/source 3 with r set = 4.7 k?. high value 2.5 ma typ low value 0.312 ma typ r set range 2.7/10 k? i cp three-state leakage current 0.2 na typ sink and source current matching 2 % typ 1.25 v v cp 2.5 v. i cp vs. v cp 1.5 % typ 1.25 v v cp 2.5 v. i cp vs. temperature 2 % typ v cp = 2.0 v. logic inputs v inh , input high voltage 1.5 v min v inl , input low voltage 0.6 v max i inh /i inl , input current 1 a max c in , input capacitance 3.0 pf max logic outputs v oh , output high voltage dv dd C 0.4 v min cmos output chosen. i oh , output high current 500 a max v ol , output low voltage 0.4 v max i ol = 500 a. power supplies av dd 3.0/3.6 v min/v max dv dd av dd v vco av dd ai dd 4 5 ma typ di dd 4 2.5 ma typ i vco 4, 5 12.0 ma typ i core = 5 ma. i rfout 4 3.5 to 11.0 ma typ rf o utput stage is programmable. low power sleep mode 4 7 a typ specifications continued on next page. footnotes on next page.
adf4360-8 rev. 0 | page 4 of 24 parameter b version unit conditions/comments rf output characteristics 5 maximum vco output frequency 400 mhz i core = 5 ma. depending on l. see the choosing the correct inductance value section. minimum vco output frequency 65 mhz vco output frequency 88/108 mhz min/max l1, l2 = 270 nh. see the choosing the correct inductance value section for other frequency values. vco frequency range 1.2 ratio f max / f min vco sensitivity 2 mhz/v typ l1, l2 = 270 nh. see the choosing the correct inductance value section for other sensitivity values. lock time 6 400 s typ to within 10 hz of final frequency. frequency pushing (open loop) 0.24 mhz/v typ frequency pulling (open loop) 10 hz typ into 2.00 vswr load. harmonic content (second) ?16 dbc typ harmonic content (third) ?21 dbc typ output power 5, 7 ?9/0 dbm typ using tuned load, programmable in 3 db steps. see table 7. output power 5, 8 ?14/?9 dbm typ using 50 ? resistors to v vco , programmable in 3 db steps. see table 7. output power variation 3 db typ vco tuning range 1.25/2.5 v min/max noise characteristics 5 vco phase noise performance 9 ?120 dbc/hz typ @ 100 khz offset from carrier. ?139 dbc/hz typ @ 800 khz offset from carrier. ?140 dbc/hz typ @ 3 mhz offset from carrier. ?142 dbc/hz typ @ 10 mhz offset from carrier. synthesizer phase noise floor 10 ?160 dbc/hz typ @ 200 khz pfd frequency. ?150 dbc/hz typ @ 1 mhz pfd frequency. ?142 dbc/hz typ @ 8 mhz pfd frequency. phase noise figure of merit 10 ?209 dbc/hz typ in-band phase noise 11, 12 ?102 dbc/hz typ @ 1 khz offset from carrier. rms integrated phase error 13 0.09 degrees typ 100 hz to 100 khz. spurious signals due to pfd frequency 12, 14 ?75 dbc typ level of unlocked signal with mtld enabled ?70 dbm typ 1 operating temperature range is C40c to +85c. 2 guaranteed by design. sample tested to ensure compliance. 3 i cp is internally modified to maintain constant loop gain over the frequency range. 4 t a = 25c; av dd = dv dd = v vco = 3.3 v. 5 unless otherwise stated , these characteristics are guaranteed for vco core power = 5 ma. l1, l2 = 270 nh, 470 ? resistors to g nd in parallel with l1, l2. 6 jumping from 88 mhz to 108 mhz. pfd frequency = 200 khz; loop bandwidth = 10 khz. 7 for more detail on using tuned loads, see output matching section. 8 using 50 ? resistors to v vco , into a 50 ? load. 9 the noise of the vco is meas ured in open-loop conditions. 10 the synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the vco and subtracting 2 0 log n (where n is the n divider value). the phase noise figure of merit subtracts 10 log (pfd frequency). 11 the phase noise is measured with the eval-adf4360-xe b1 evaluation board and the hp 8562e sp ectrum analyzer. th e spectrum analy zer provides the refin for the synthesizer; offset frequency = 1 khz. 12 f refin = 10 mhz; f pfd = 200 khz; n = 1000; loop b/w = 10 khz. 13 f refin = 10 mhz; f pfd = 1 mhz; n = 120; loop b/w = 100 khz. 14 the spurious signals are meas ured with the eval-adf4360- xeb1 evaluation board and the hp 8562e spectrum analyzer. the spectrum analyzer provides the refin for the synthesizer; f refout = 10 mhz @ 0 dbm.
adf4360-8 rev. 0 | page 5 of 2 4 timing characteristics av dd = d v dd = v vc o = 3.3 v 10%; a g nd = d g nd = 0 v ; 1. 8 v a nd 3 v log i c lev e l s us ed; t a = t min to t max , u n l e s s o t h e r w i s e n o t e d . table 2. parameter limit at t min to t ma x (b version ) unit test condition s /comments t 1 20 ns min le setup time t 2 10 ns min data to clock setup time t 3 10 ns min data to clock hold time t 4 25 ns min clock high duration t 5 25 ns min clock low duration t 6 10 ns min clock to le set u p time t 7 20 ns min le pulse width cloc k data le le db23 (msb) db22 db2 db1 (control bit c2) db0 (lsb) (control bit c1) t 1 t 2 t 3 t 7 t 6 t 4 t 5 04763-002 f i g u re 2. ti ming d i ag r a m
adf4360-8 rev. 0 | page 6 of 2 4 absolute maximum ratings t a = 2 5 c , u n l e ss ot he r w i s e not e d. table 3. p a r a m e t e r r a t i n g av dd to gnd 1 ?0.3 v to +3.9 v av dd to dv dd ?0.3 v to +0.3 v v vco to gnd ?0.3 v to +3.9 v v vco to av dd ?0.3 v to +0.3 v digital i/o voltage to gnd ?0.3 v to v dd + 0.3 v analog i/o voltage to gnd ?0.3 v to v dd + 0.3 v ref in to gnd ?0.3 v to v dd + 0.3 v operating temperature range ?40c to + 85c storage temperature range ?65c to +150c maximum junction temperature 150c csp ja thermal impedance paddle soldered 50c/w paddle not soldered 88c/w lead temperature, soldering vapor phase (60 sec) 215c infrared (15 sec) 220c 1 gnd = agnd = dgnd = 0 v. s t r e s s es a b o v e t h os e lis t e d u n de r a b s o l u t e m a xi m u m r a t i n g s ma y c a us e p e r m a n en t dama ge t o t h e de vice . this is a s t r e s s ra t i n g onl y ; f u n c t i o n al o p era t ion o f t h e de vice a t t h es e o r an y o t h e r con d i t io ns a b o v e t h os e list e d i n t h e o p era t io nal s e c t io n s o f t h is sp e c if ic a t io n is n o t i m pli e d . e x p o sur e t o a b s o l u t e m a xi- m u m r a t i n g condi t i on s fo r ex ten d e d p e r i o d s m a y a f fe c t de vice rel i a b i l it y . this de vice is a hig h p e r f o r ma n c e rf in t e g r a t e d cir c ui t wi t h an e s d r a t i ng of < 1 k v , a n d it i s e s d s e ns it ive. pr op e r pre c aut i on s s h o u ld b e ta k e n f o r ha n d lin g and as s e m b l y . transis t o r count 12543 (cm o s) a nd 700 (b i p ol ar) esd caution esd (electrostatic discharge) sensitive device. ele c trosta tic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge without detection. although this product features proprie - tary esd protect i on circuitry, permanent damag e may o ccur on devices subje c ted to high energy electrostatic discharges. ther efore, prop er esd precautions a r e reco mmende d to avoid performance degradation or lo ss of functionality.
adf4360-8 rev. 0 | page 7 of 2 4 pin conf iguration and fu nction descriptions adf4360-8 top view (not to scale) cpgnd 1 av dd 2 agnd 3 rf out a 4 rf out b 5 v vco 6 data 18 clk 17 ref in 16 dgnd 15 c n 14 r set 13 v tune 7 agnd 8 l1 9 l2 10 agnd 11 c c 12 cp 24 ce 23 agnd 22 dv dd 21 mux o u t 20 le 19 04763-003 pin 1 identifier f i gure 3. pin config ur ation ta ble 4. pi n f u nct i on d e s c ri pt i o ns pin no. mnemonic function 1 cp gnd charge p u mp ground. t h is is the ground return path for the c h arge pump. 2 a v dd anal og p o w e r supply. t h is ranges from 3.0 v to 3.6 v. decoup ling capacitors to the a n alog ground p l a n e should be placed as close a s possible to this pin. av dd must have the same value as dv dd . 3, 8, 11, 22 agnd analog grou nd. this is the gr ound return path of the presc a l e r and vco. 4 r f ou t a vco output. the output leve l is pr ogrammable fro m 0 dbm to ? 9 d b m. see the out p ut matchi ng sec t ion for a description of the various output stages. 5 r f ou t b vco compl e mentary output. t h e output l e vel is pr ogramma ble fro m 0 dbm to ?9 d b m. see the out p ut matchi ng section for a description of the various output stages. 6 v vco po wer supp ly for the vco. this ranges from 3.0 v to 3.6 v. d e coupl i ng c a pac i tors to the anal og ground pl ane shoul d be pla c ed as clos e as possible to t h is pin. v vco must have the same value as av dd . 7 v tu n e control i n put to t h e vco. this vo lt age determines the output freque ncy and is derive d from filtering t h e cp output voltage. 9 l1 an externa l indu ctor to a g nd should be connect e d to this pin t o set the a d f43 60-8 output frequen c y. l1 and l 2 need to be t h e same value. a 470 ? resistor should be added in parallel to a g nd. 1 0 l 2 an externa l indu ctor to a g nd sh ould be con n ect e d to th is pin t o set the a d f43 60-8 output frequen c y. l1 and l 2 need to be t h e same value. a 470 ? resistor should be added in parallel to a g nd. 1 2 c c internal compensation node. t h is pin must be decoupled t o ground with a 10 nf ca pacitor. 1 3 r set connecting a resistor between thi s pin and cp gnd s e ts the maximum c h arge pump output c u rrent for the synthesizer. the n o m i na l v o lt a g e potentia l a t t h e r set pin is 0.6 v. the relationshi p bet w een i cp and r set is set cpmax r i = where r set = 4.7 k ? , i cpm a x = 2.5 ma. 1 4 c n internal compensation node. t h is pin must be decoupled t o v vco with a 10 f capaci tor. 15 dgn d dig i ta l gr ound. 1 6 r e f in reference input. this is a cmos input wit h a nominal thresho l d of v dd / 2 and a dc equi val e nt input resis tanc e of 100 k? (see figure 16). this input can be driven from a ttl or cmos crystal osci llator, or it can be ac -c oupled. 17 clk serial cl ock input. t h is serial c l ock is used to c l oc k i n the serial data to the registers. the data is latche d into th e 24-bit shift register on the clk rising edge. this input is a high impedance cmos input. 18 d a t a serial d a ta input. t h e serial data is l o aded msb firs t with t h e two lsb s being the contr o l bits. this input is a high impedance cmos input. 19 le load enable, cmos inpu t. when l e goes high, the data stored in the shift registers is loaded into o n e of the four la tches, a n d t h e r e lev a nt la t c h is s e lected u sing t h e contr o l bits. 20 muxou t this m u ltip lexer ou tpu t a l lo ws either the lo ck dete ct, the sca l ed rf, or the scaled referenc e frequenc y to be a ccessed exter n a lly. 2 1 d v dd d i gital p o w e r su pply. t h is ranges from 3.0 v to 3.6 v. decoup ling capacitors to the di gital ground plan e should be placed as close a s possible to this pin. dv dd must have the same value as av dd . 23 c e c h ip ena b le. a l o g i c lo w on t h is pi n po wer s dow n t h e devic e and pu ts the c h arge pu mp into three- state mode. taking the pin hi gh po wers up th e device depe ndi n g on the status of the po wer-do wn bits. 2 4 c p ch arge p u mp o u tp u t . wh en e n abl e d , th i s p r o v id e s i cp to t h e e x ter n a l loo p fi lter, whi c h i n t u rn dri v es t h e i n t e rna l vc o.
adf4360-8 rev. 0 | page 8 of 2 4 typical perf orm ance cha r acte ristics ?150 ?120 ?130 ?140 ?7 0 ?6 0 ?9 0 ?100 ?110 ?8 0 ?4 0 ?5 0 100 1k 10k 100k 1m 10m frequency offset (hz) outp ut p o w e r (db) 04763-004 f i gure 4. o p en-l o o p vc o p h ase n o ise , l1, l 2 = 5 6 0 n h ?150 ?125 ?130 ?120 ?135 ?140 ?145 ?8 5 ?8 0 ?9 5 ?100 ?105 ?110 ?115 ?9 0 ?7 0 ?7 5 100 1k 10k 100k 1m 10m frequency offset (hz) outp ut p o w e r (db) 04763-005 f i g u re 5. v c o p h as e n o is e , 65 m h z, 1 m h z pfd , 10 0 k h z l oop b a ndw i dt h 04763-006 outp ut p o w e r (db) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 ?2khz ? 1khz 65mhz 1khz 2khz ?107.4dbc/hz reference level = ? 2.5dbm v dd = 3.3v, v vco = 3.3v i cp = 2.5ma pfd frequency = 1mhz loop bandwidth = 100khz res. bandwidth = 30hz video bandwidth = 30hz sweep = 1.9seconds averages = 20 f i g u re 6. cl os e - in phas e n o is e at 6 5 m h z ( 1 m h z ch ann e l spac ing ) 04763-007 outp ut p o w e r (db) ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 ?2 0 ?1 0 0 ? 1.1mhz ?0.55mhz 65mhz 0.55mhz 1.1mhz ? 84dbc reference level = ? 2.5dbm v dd = 3 . 3 v, v vc o =3 . 3 v i cp =2 . 5 m a pf d f r e q u en c y = 1 mh z l o o p band w i dt h = 100 khz re s . bandw i d t h = 1 khz v i de o bandw i d t h = 1 khz sw eep = 4 . 2 sec o n d s a ver a g es = 2 0 f i g u re 7. r e f e r e n c e spurs at 65 m h z (1 mh z ch anne l sp ac ing , 100 kh z l oop bandw i dth) ?150 ?120 ?130 ?140 ?7 0 ?6 0 ?9 0 ?100 ?110 ?8 0 ?4 0 ?5 0 100 1k 10k 100k 1m 10m frequency offset (hz) outp ut p o w e r (db) 04763-008 f i gure 8 . o p en-l oop vc o p h a s e noi s e , l1 , l 2 = 11 0 n h ?150 ?125 ?130 ?120 ?135 ?140 ?145 ?8 5 ?8 0 ?9 5 ?100 ?105 ?110 ?115 ?9 0 ?7 0 ?7 5 100 1k 10k 100k 1m 10m frequency offset (hz) outp ut p o w e r (db) 04763-009 f i g u re 9. v c o p h as e n o is e , 16 0 m h z, 1 m h z pfd , 10 0 k h z l oop b a ndw i dt h
adf4360-8 rev. 0 | page 9 of 2 4 04763-010 outp ut p o w e r (db) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 ?2khz ? 1khz 160mhz 1khz 2khz ?109.4dbc/hz reference level = 1dbm v dd = 3.3v, v vco = 3.3v i cp = 2.5ma pfd frequency = 1mhz loop bandwidth = 100khz res. bandwidth = 30hz video bandwidth = 30hz sweep = 1.9seconds averages = 20 f i g u re 10. cl os e - in p h as e n o is e at 1 6 0 m h z ( 1 m h z ch ann e l sp ac ing ) 04763-011 outp ut p o w e r (db) ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 ?2 0 ?1 0 0 ? 1.1mhz ?0.55mhz 160mhz 0.55mhz 1.1mhz ? 76dbc reference level = 1dbm v dd = 3 . 3 v, v vc o =3 . 3 v i cp =2 . 5 m a pf d f r e q u en c y = 1 mh z l o o p band w i dt h = 100 khz re s . bandw i d t h = 1 khz v i de o bandw i d t h = 1 khz sw eep = 4 . 2 sec o n d s a ver a g es = 2 0 f i gure 11. r e ference spurs at 1 6 0 mh z (1 mh z ch anne l sp ac ing , 100 kh z l oop bandw i dth) ?150 ?120 ?130 ?140 ?7 0 ?6 0 ?9 0 ?100 ?110 ?8 0 ?4 0 ?5 0 100 1k 10k 100k 1m 10m frequency offset (hz) outp ut p o w e r (db) 04763-012 f i gure 12. o p en-l oop vc o p h as e n o is e , l 1 , l 2 = 18 n h ?150 ?125 ?130 ?120 ?135 ?140 ?145 ?8 5 ?8 0 ?9 5 ?100 ?105 ?110 ?115 ?9 0 ?7 0 ?7 5 100 1k 10k 100k 1m 10m frequency offset (hz) outp ut p o w e r (db) 04763-013 f i gure 13. vc o pha s e no ise , 4 0 0 mh z, 1 mh z pfd , 1 0 0 kh z l oop band width 04763-014 outp ut p o w e r (db) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 ?2khz ? 1khz 400mhz 1khz 2khz ?103.4dbc/hz reference level = 0dbm v dd = 3.3v, v vco = 3.3v i cp = 2.5ma pfd frequency = 1mhz loop bandwidth = 100khz res. bandwidth = 30hz video bandwidth = 30hz sweep = 1.9seconds averages = 20 f i g u re 14. cl os e - in p h as e n o is e at 4 0 0 m h z ( 1 m h z ch ann e l sp ac ing ) 04763-015 outp ut p o w e r (db) ?9 0 ?8 0 ?7 0 ?6 0 ?5 0 ?4 0 ?3 0 ?2 0 ?1 0 0 ? 1.1mhz ?0.55mhz 400mhz 0.55mhz 1.1mhz ? 77dbc reference level = 0dbm v dd = 3 . 3 v, v vc o =3 . 3 v i cp =2 . 5 m a pf d f r e q u en c y = 1 mh z l o o p band w i dt h = 100 khz re s . bandw i d t h = 1 khz v i de o bandw i d t h = 1 khz sw eep = 4 . 2 sec o n d s a ver a g es = 2 0 f i gure 15. r e ference spurs at 4 0 0 mh z (1 mh z ch anne l sp ac ing , 100 kh z l oop bandw i dth)
adf4360-8 rev. 0 | page 10 of 24 circuit description reference input section the r e fer e n c e i n p u t s t a g e is sho w n i n f i gur e 1 6 . sw1 an d s w 2 a r e n o r m al ly clos e d s w i t ch es. sw3 is n o r m al ly o p en. w h e n p o w e r - do w n is i n i t ia te d , sw3 is clo s e d , a nd s w 1 a nd sw2 a r e o p ene d . this ens u r e s t h a t t h er e is n o lo adin g o f t h e ref in pi n on p o we r - d o w n . 04763-016 buffer to r counter ref in 100k ? nc sw2 sw3 no nc sw1 power-down control f i gure 16. r e ference input stag e n cou n ter t h e cm os n co un t e r allo ws a wide d i visio n ra tio in t h e p ll fe e d b a ck co un ter . th e co u n t e rs a r e s p e c if ie d t o w o rk w h e n th e v c o o u t p u t is 400 mh z o r les s . t o a v oid conf usio n, this is re fe r r e d to as t h e b c o u n te r . i t ma k e s i t p o ss ibl e to ge ne r a te o u t p u t f r eq ue n c i e s th a t a r e s p aced o n l y b y th e r e f e r e n c e f r e q uen c y divid e d b y r . t h e v c o f r eq ue n c y eq ua ti o n i s r f b f refin vco / = w h er e: f vc o i s th e o u t p u t f r eq ue n c y o f th e v c o . b is t h e p r es et di vide r a t i o of t h e bi n a r y 1 3 - bit c o u n t e r ( 3 to 8 1 9 1 ) . f refin is t h e ext e r n al r e fer e n c e f r e q uen c y os ci l l a t or . r counter t h e 14-b i t r co un t e r allo w s th e i n p u t r e f e r e n c e f r eq ue n c y t o b e divide d do w n t o p r o d uce t h e r e fer e n c e clo c k t o t h e phas e f r eq uen c y det e c t o r (p fd). di vis i o n ra tios f r o m 1 t o 16,383 a r e allo w e d . pf d an d c h arge pump the p f d t a k e s i n p u ts f r o m t h e r co un t e r and n co un t e r ( n = bp + a ) an d pr o d u c e s a n output prop or t i on a l to t h e ph a s e a n d f r e q uen c y dif f er en c e b e tw e e n t h em. f i gur e 17 is a sim p lif i e d s c h e ma t i c. th e p f d i n cl udes a p r og ra mma b l e de l a y e l e m e n t tha t con t r o ls the wid t h o f t h e an tibacklas h p u ls e . this p u ls e en s u r e s t h a t t h e r e is n o de ad zon e i n t h e p f d t r a n sfer f u n c t i o n a nd mi nimi zes phas e n o is e and r e fer e n c e s p urs. t w o b i t s in t h e r co un t e r l a t c h, ab p2 and a b p 1 , co n t r o l t h e wi d t h o f t h e p u ls e (see t a b l e 9). 04763- 017 programmable delay u3 clr2 q2 d2 u2 clr1 q1 d1 charge pump down up hi hi u1 abp1 abp2 r divider n divider c p outpu t r divider n divider cp cpgnd v p f i gur e 1 7 . p f d simpl i f ie d s c hema ti c and t i mi ng (in l o c k ) muxout a n d loc k de tect the o u t p u t m u l t i p lexer o n th e ad f4360 fa mily al lo ws th e us er t o acces s va r i o u s in t e r n al p o in ts o n t h e chi p . the s t a t e o f mux o ut is con t r o l l ed b y m3, m2, a nd m1 in t h e f u n c tion la t c h. th e f u l l t r u t h t a b l e is sh o w n in t a b l e 7. f i gur e 18 s h o w s t h e m u x o u t s e c t io n i n b l o c k di a g r a m fo r m . r counter output n counter output digital lock detec t dgnd control mux muxout dv dd 04763-018 f i g u re 18. m u x o u t ci r c u i t
adf4360-8 rev. 0 | page 11 of 24 lock det e ct t h e co rr ect ba n d i s c h osen a u t o m a ti call y b y th e ba n d s e lect log i c a t p o w e r - up o r w h e n e v er t h e n co un t e r l a tch is u p da t e d . i t i s i m po r t a n t tha t th e co rr ect w r i t e seq u en ce b e f o llo w ed a t p o w e r - u p . this s e q u e n ce is mux o ut can be p r ogra mm e d f o r o n e typ e o f lo c k d e t e c t . dig i t a l lo ck dete c t is ac t i v e hig h . w h en ld p in t h e r co u n t e r l a tch i s s e t to 0, di g i t a l l o ck de te c t i s s e t hi g h w h en t h e phas e er ro r o n th r e e co n s e c u t i v e ph ase de t e ct o r c y c l es is les s tha n 15 n s . 1. r c o u n te r l a tc h w i t h ld p s e t t o 1, f i v e co n s ec u t i v e c y c l es o f les s tha n 15 n s phas e er r o r a r e r e q u ir e d t o s e t t h e lo ck dete c t . i t s t a y s s e t hig h un til a p h a s e e r r o r o f gr ea t e r th a n 25 n s i s d e t e ct ed o n a n y subs e q u e n t pd c y cl e. 2. c o n t r o l la t c h 3. n c o u n te r l a tch d u r i n g b a n d s e l e c t , w h i c h t a k e s f i v e p f d c y c l e s , t h e v c o v tun e i s d i s c on ne c t e d f rom t h e output of t h e l o op f i lte r and c o n n e c t e d to an i n te r n a l re fe re nc e volt age. inpu t shift register the ad f4360 f a mil y s dig i tal s e c t io n in c l udes a 24-b i t in p u t s h if t r e g i st er , a 14-b i t r co u n t e r , a nd an 18-b i t n co un t e r co m p r i s e d o f a 5-b i t a co un ter a nd a 13 -b i t b c o un t e r . d a t a is c l oc k e d in t o th e 24- b i t s h i f t r e gis t e r o n ea ch ri s i n g ed g e o f c l k . the da t a is c l o c k e d in ms b f i r s t. da t a is tra n sf er r e d f r o m th e s h if t r e g i st er t o o n e o f fo ur la t c h e s on t h e r i sin g e d g e o f le. th e des t ina t io n la t c h is det e r m i n e d b y t h e s t a t e o f t h e tw o co n t r o l b i ts (c2, c1) in t h e shif t r e g i st er . th es e a r e t h e t w o ls bs, d b 1 a nd db0, sh o w n in f i gur e 2. 0 1.0 0.5 2.5 2.0 1.5 3.5 3.0 80 85 90 100 95 105 115 110 frequency (mhz) v tune (v ) 04763-019 the t r u t h t a b l e fo r t h es e b i ts is s h own i n t a b l e 5. t a b l e 6 s h o w s a s u mma r y o f ho w t h e l a t c h e s ar e p r og ra mm e d . n o t e t h a t t h e te st mo de s l a tch i s u s e d for f a c t or y te st i n g and shou l d not b e p r ogra m m e d b y th e user . table 5. c2 an d c1 truth ta ble fi u r e 1 9 . fr e u e n c v s . v t n d f4 3 60 8 l 1 a n d l2 2 70 n control bits c2 c1 data latch 0 0 control latch 0 1 r counter 1 0 n counter (b) 1 1 test modes latc h t h e r co un t e r o u t p u t i s used as th e c l ock f o r th e ba n d s e lect log i c a n d sh o u l d n o t exce e d 1 mh z. a p r og ra mma b l e divider is p r o v ided a t t h e r co un t e r in p u t t o al lo w di visio n b y 1, 2, 4, o r 8 a nd is co n t r o l l e d b y b i ts bsc1 a nd bsc2 i n t h e r co un ter la t c h. w h er e t h e r e q u ir e d p f d f r e q ue n c y exce e d s 1 mh z, t h e divide ra t i o s h o u ld b e s et t o al lo w en oug h t i m e fo r co r r e c t b a n d se l e cti o n . vco the v c o co r e in the ad f4360 fa mil y us es eig h t o v erla p p i n g ba nds, as sh o w n in f i gur e 19, t o al lo w a wide f r eq uen c y ra n g e t o b e c o ve re d w i t h out a l a r g e v c o s e ns it i v it y ( k v ) a nd r e su l t an t p o o r phas e n o is e a nd s p ur io us p e r f o r ma n c e . a f te r b a n d s e l e c t i o n , nor m a l p l l a c t i on re su me s . t h e v a lu e of k v is det e r m in e d b y th e val u e o f in d u c t o r s us e d (s ee the ch o o sin g t h e c o r r ec t i n d u c t ance v a l u e s e c t ion). th e ad f4360 fa m i l y co n t a i n s lin e a r iz a t io n cir c ui tr y t o m i n i mize a n y va r i a t io n o f t h e p r o d uc t of i cp and k v . the o p er a t in g c u r r en t in t h e v c o co r e is p r og ra mma b l e i n fo ur s t eps: 2.5 ma, 5 ma, 7.5 ma, and 10 ma. this is co n t r o l l ed b y b i ts pc1 and p c 2 in t h e con t rol la t c h.
adf4360-8 rev. 0 | page 12 of 24 outpu t st age the rf ou t a a nd rf ou t b p i n s o f th e ad f4360 f a mil y a r e co nnec t e d t o t h e co l l ec t o r s o f a n np n dif f er en tial p a ir dr i v en by bu f f e r e d output s of t h e v c o , a s show n i n f i g u re 2 0 . t o a l l o w t h e us er t o o p t i mi ze t h e p o w e r dis s i p a t io n v e rsus t h e o u t p u t p o w e r r e q u ir emen ts, t h e t a i l c u r r en t o f t h e dif f er en t i al p a ir is p r og ra mma b l e v i a b i ts p l 1 and p l 2 in t h e con t r o l la t c h. f o ur c u r r en t lev e ls ma y be s et: 3.5 ma, 5 ma, 7.5 ma, a nd 11 ma. th es e leve ls g i ve o u t p u t p o w e r lev e ls o f ?9 db m, ?6 db m, ?3 dbm, an d 0 dbm, r e sp e c t i vely , usin g t h e co r r e c t sh un t ind u c t o r t o v dd a nd ac co u p li n g in to a 50 ? lo ad . a l ter n a t i v ely , bo th o u t p u t s c a n b e com b in e d in a 1 + 1:1 tra n s f o r m e r o r a 180 m i cr os tri p co u p le r (see th e ou t p u t m a t c hi n g se cti o n ) . i f th e o u t p u t s a r e used in di v i d u all y , th e o p tim u m o u t p u t s t a g e co n s is ts o f a sh un t i n d u c t o r t o v dd . an o t h e r fe a t ur e o f t h e ad f4360 fa mi l y i s tha t t h e s u p p l y c u rr en t t o th e r f o u t p u t s t a g e i s s h u t d o w n un til th e pa r t a c h i ev e s loc k a s m e a s ur ed b y th e d i gi tal loc k d e t e ct ci r c ui t r y . t h i s i s e n a b led b y th e m u te - t i l l - l o ck d e te c t ( m tl d ) b i t i n t h e c o n t rol l a tch. vco rf out ar f out b buf f e r/ di v i de by 2 04763-020 f i g u re 20. o u t p ut s t ag e a d f4 3 60- 8
adf4360-8 rev. 0 | page 13 of 24 latch structure t a b l e 6 sh o w s th e thr e e on-chi p la t c h e s f o r the ad f4360 fa mily . th e tw o ls bs decide which la t c h is p r og ra mm e d . table 6. latch structure db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (0) pc1 pc2 cr m1 m2 pdp cp cpg mtld pl1 pl2 cpi1 cpi2 cpi3 cpi4 cpi5 cpi6 pd1 m3 c o nt ro l bi t s mux o u t c o nt ro l curr e n t se t t in g 2 curr e n t se t t in g 1 core power level output power level db21 db22 db23 power- down 2 reserved reserved reserved reserved power- down 1 counter reset mute- t il- ld cp gain cp t hree- st at e phase det e ct or pol arit y pd2 rsv rsv db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (1) r1 r2 r3 r4 r5 r7 r8 r9 r10 r11 r12 r13 r14 abp1 abp2 ldp tmb bsc1 r6 c o nt ro l bi t s b and se l e c t cl o c k ant i - back la s h pu l s e wi dt h 14-bit reference counter db21 db22 db23 loc k det e ct precision t est mode bit reserved reserved bsc2 rsv rsv rsv rsv db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (1) c1 (0) rsv rsv rsv rsv rsv b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 rsv c o nt ro l bi t s reserved 13-bit b counter control latch n counter latch r counter latch db21 db22 db23 cp gain cpg 04763-021
adf4360-8 rev. 0 | page 14 of 24 table 7. co ntrol latch db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (0) pc1 pc2 cr m1 m2 pdp cp cpg mtld pl1 pl2 cpi1 cpi2 cpi3 cpi4 cpi5 cpi6 pd1 m3 co ntro l bi ts mu x o ut co ntro l c urre n t s e tti n g 2 c urre n t s e tti n g 1 core power level output power level db21 db22 db23 power- down 2 power- down 1 count er reset mute-til- ld reserved reserved cp gain cp three- state phase det e ct o r po l arit y pd2 rsv rsv cr 0 1 counter operation normal r, a, b counters held in reset pc2 0 0 10 c o r e po w e r l evel 2. 5ma 5m a 7. 5ma pc1 0 1 11 10m a cp 0 1 charge pump output normal three-state pdp 0 1 phase detector polarity ne g a t i v e po si t i v e cpg 0 1 cp gain curre nt s e t t i n g 1 curre nt s e t t i n g 2 mtld 0 1 mute-til-lock detect di s abl e d e nabl e d m3 m2 m1 mu xo u t three-state output 00 0 00 1 01 0 01 1 10 0 10 1 11 0 11 1 digital lock detect (active high) n divider output dv dd r divider output not used n o t u sed dgnd ce pin pd2 pd1 mode 0 x x asynchronous power-down 1 x 0 normal operation 1 0 1 asynchronous power-down 1 1 1 synchronous power-down cpi6 cpi5 cpi4 i cp (ma) cpi3 cpi2 cpi1 4.7k ? 0.31 0.62 0.93 1.25 1.56 1.87 2.18 2.50 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 pl2 pl1 output power level current (using tuned load) ?9dbm ?6dbm ?3dbm 0dbm (using 50 ? to v vco ) ? 19dbm ? 15dbm ? 12dbm ? 9dbm 0 0 1 1 0 1 0 1 3.5ma 5.0ma 7.5ma 11.0ma 04763-022 these bits are not used by the device and are don't care bits.
adf4360-8 rev. 0 | page 15 of 24 tab l e 8. n cou n ter latch db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (1) c1 (0) rsv rsv rsv rsv rsv b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 rsv c o nt ro l bi ts reserved 13-bit b counter db21 db22 db23 cp g a in reserved reserved cpg rsv rsv f4 (function latch) fastlock enable cp gain operation charge pump current setting 1 is permanently used 0 0 charge pump current setting 2 is permanently used 1 0 n = b; p is prescaler value set in the control latch. b must be greater than or equal to a. for continuously adjacent values of (n f ref ), at the output, n min is (p 2 ?p). b13 b12 b11 b3 b2 b1 b counter divide ratio .......... 0 00 0 00 0 00 0 00 0 0 0 not allowed .......... 0 0 1 not allowed .......... 0 1 0 not allowed .......... 1 1 1 3 .......... . .. . .. . .. . .. . .......... . . . . .......... . . . . .......... 1 11 1 11 1 11 1 11 1 0 0 8188 .......... 1 0 1 8189 .......... 1 1 0 8190 .......... 1 1 1 8191 04763-023 these bits are not used by the device and are don't care bits. these bits are not used by the device and are don't care bits.
adf4360-8 rev. 0 | page 16 of 24 tab l e 9. r cou n ter latch db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (1) r1 r2 r3 r4 r5 r7 r8 r9 r10 r11 r12 r13 r14 abp1 abp2 ldp tmb bsc1 r6 co n t ro l bi t s ba nd se l e c t clo c k an t i - ba ck las h pu l s e wi dt h 14-bit reference counter db21 db22 db23 lo ck detect precision test mode bit reserved reserved bsc2 rsv rsv test mode bit should be set to 0 for normal operation. r14 r13 r12 r3 r2 r1 divide ratio .......... 0 00 0 00 0 00 0 00 0 01 1 .......... 0 1 0 2 .......... 0 1 1 3 .......... 1 0 0 4 .......... . .. . .. . .. . .. . .......... . . . . .......... . . . . .......... 1 11 1 11 1 11 1 11 1 0 0 16380 .......... 1 0 1 16381 .......... 1 1 0 16382 .......... 1 1 1 16383 these bits are not used by the device and are don't care bits. 04763- 024 ldp lock detect precision 0 three consecutive cycles of phase delay less than 15ns must occur before lock detect is set. 1 five consecutive cycles of phase delay less than 15ns must occur before lock detect is set. abp2 abp1 antibacklash pulse width 0 0 3.0ns 0 1 1.3ns 1 0 6.0ns 1 1 3.0ns bsc2 bsc1 band select clock divider 00 1 01 2 10 4 11 8
adf4360-8 rev. 0 | page 17 of 24 control latch with (c2, c1) = (0,0), the control latch is programmed. table 7 shows the input data format for programming the control latch. power-down db21 (pd2) and db20 (pd1) provide programmable power- down modes. in the programmed asynchronous power-down, the device powers down immediately after latching a 1 into bit pd1, with the condition that pd2 has been loaded with a 0. in the programmed synchronous power-down, the device power- down is gated by the charge pump to prevent unwanted frequency jumps. once the power-down is enabled by writing a 1 into bit pd1 (on the condition that a 1 has also been loaded to pd2), the device goes into power-down on the second rising edge of the r counter output, after le goes high. when the ce pin is low, the device is immediately disabled regardless of the state of pd1 or pd2. when a power-down is activated (either synchronous or asynchronous mode), the following events occur: ? all active dc current paths are removed. ? the r, n, and timeout counters are forced to their load state conditions. ? the charge pump is forced into three-state mode. ? the digital lock detect circuitry is reset. ? the rf outputs are debiased to a high impedance state. ? the reference input buffer circuitry is disabled. ? the input register remains active and capable of loading and latching data. charge pump currents cpi3, cpi2, and cpi1 in the adf4360 family determine current setting 1. cpi6, cpi5, and cpi4 determine current setting 2. see the truth table in table 7 . output power level bits pl1 and pl2 set the output power level of the vco. see the truth table in table 7 . mute-till-lock detect db11 of the control latch in the adf4360 family is the mute- till-lock detect bit. this function, when enabled, ensures that the rf outputs are not switched on until the pll is locked. cp gain db10 of the control latch in the adf4360 family is the charge pump gain bit. when it is programmed to 1, current setting 2 is used. when it is programmed to 0, current setting 1 is used. charge pump three-state this bit puts the charge pump into three-state mode when programmed to a 1. it should be set to 0 for normal operation. phase detector polarity the pdp bit in the adf4360 family sets the phase detector polarity. the positive setting enabled by programming a 1 is used when using the on-chip vco with a passive loop filter or with an active noninverting filter. it can also be set to 0, which is required if an active inverting loop filter is used. muxout control the on-chip multiplexer is controlled by m3, m2, and m1. see the truth table in table 7 . counter reset db4 is the counter reset bit for the adf4360 family. when this is 1, the r counter and the a, b counters are reset. for normal operation, this bit should be 0. core power level pc1 and pc2 set the power level in the vco core. the recom- mended setting is 5 ma. see the truth table in table 7.
adf4360-8 rev. 0 | page 18 of 24 n counter latch table 8 shows the input data format for programming the n counter latch. reserved bits db2 to db7 are spare bits and have been designated as reserved. they should be programmed to 0. b counter latch b13 to b1 program the b counter. the divide range is 3 (00.....0011) to 8191 (11....111). overall divide range the overall vco feedback divide range is defined by b. cp gain db21 of the n counter latch in the adf4360 family is the charge pump gain bit. when this is programmed to 1, current setting 2 is used. when programmed to 0, current setting 1 is used. this bit can also be programmed through db10 of the control latch. the bit always reflects the latest value written to it, whether this is through the control latch or the n counter latch. r counter latch with (c2, c1) = (0, 1), the r counter latch is programmed. table 9 shows the input data format for programming the r counter latch. r counter r1 to r14 set the counter divide ratio. the divide range is 1 (00......001) to 16383 (111......111). antibacklash pulse width db16 and db17 set the antibacklash pulse width. lock detect precision db18 is the lock detect precision bit. this bit sets the number of reference cycles with less than 15 ns phase error for entering the locked state. with ldp at 1, five cycles are taken; with ldp at 0, three cycles are taken. test mode bit db19 is the test mode bit (tmb) and should be set to 0. with tmb = 0, the contents of the test mode latch are ignored and normal operation occurs as determined by the contents of the control latch, r counter latch, and n counter latch. note that test modes are for factory testing only and should not be programmed by the user. band select clock these bits set a divider for the band select logic clock input. the output of the r counter is by default the value used to clock the band select logic, but if this value is too high (>1 mhz), a divider can be switched on to divide the r counter output to a smaller value (see table 9). reserved bits db23 to db22 are spare bits that have been designated as reserved. they should be programmed to 0.
adf4360-8 rev. 0 | page 19 of 24 choos ing the corre ct inductance value the ad f4360-8 ca n be us e d a t ma n y dif f er en t f r eq uen c ies sim p ly b y ch o o sin g t h e ext e r n al ind u c t o r s t o g i ve t h e co r r e c t output f r e q u e nc y . f i g u re 2 1 show s a g r a p h of b o t h m i n i m u m a nd max i m u m f r e q uen c y versus t h e ex ter n a l i n d u c t o r va l u e. the co r r e c t ind u c t o r sh o u ld cover t h e max i m u m an d min i m u m f r eq uen c ies desir e d . th e ind u c t o r s us ed a r e 0603 cs o r 0805 cs t y pe f r o m c o il cra f t . t o r e d u ce m u t u al c o u p li n g , th e in d u ct o r s s h o u ld b e place d a t r i g h t a n g l es t o o n e an o t h e r . the lo w e st cen ter f r e q uen c y o f os ci l l a t ion p o ssib le is a p p r o x i- ma te l y 65 mh z, whic h is ac hieved usin g 560 nh ind u c t o r s. this r e la t i on s h i p can b e exp r es s e d b y () ext o l f + = nh 0.9 pf 9.3 2 1 0 150 50 100 350 250 300 200 450 400 0 100 200 300 400 600 500 inductance (nh) fre q ue ncy (mhz) 04763-025 f i gure 21. o u tput c e nte r f r equ e nc y vs. ex tern al induc t or v a lu e w h er e f o is t h e cen t er f r e q ue n c y a n d l ex t is t h e ext e r n a l ind u c - t a nce . th e a p p r o x ima te val u e of ca p a ci t a n c e a t t h e mid p o i n t o f t h e ce n t er b a nd o f t h e v c o is 9. 3 pf , a n d t h e a p p r o x ima te val u e o f in t e r n al i n d u c t a n c e d u e t o t h e b o nd wir e s is 0.9 nh. th e v c o s e n s i t ivi t y is a m e as ur e o f th e f r eq uen c y c h a n g e v e rs us the t u n i n g v o l t a g e . i t i s a v e r y i m po r t a n t pa ra m e t e r f o r th e l o w - pa s s f i l t er . f i gur e 22 sh o w s a g r a p h of t h e t u nin g s e nsi t ivi t y ( i n mh z/v) v e rs us t h e i n d u c t an c e (nh). i t ca n b e s e en t h a t as t h e i n d u cta n ce in cr ea se s , th e se n s i t i v i t y d e cr ea se s . t h i s r e la ti o n s h i p ca n b e der i ve d f r o m t h e e q u a t i on a b o v e, i . e., si nce t h e i n d u c - t a nce has in cr e a s e d , t h e cha n ge in c a p a ci t a n c e f r o m t h e v a rac t or has les s o f a n ef f e c t o n the f r eq uen c y . 0 4 2 10 8 6 12 0 100 200 300 400 600 500 inductance (nh) sen sitivity ( m h z /v) 04763-026 f i g u re 22. t u n i ng s e ns it iv it y ( i n m h z / v ) v s . induc t anc e ( n h) fixe d freq uency l o f i gur e 23 s h o w s th e ad f4360-8 us ed as a f i xe d f r eq uen c y l o a t 200 mh z. the lo w-p a s s f i l t er was desig n ed usin g ad i s imp l l fo r a cha nnel sp acin g o f 2 mhz a nd an o p e n -lo o p b a ndwi d t h of 100 kh z. th e maxim u m p f d f r eq uen c y o f the ad f4360-8 is 8 mh z. s i n c e usin g a la rg er p f d f r eq uen c y al lo ws th e us e o f a smal ler n, t h e i n -b and phas e no is e is r e d u ce d to as lo w as p o s s i b l e , ?109 db c/h z . th e typ i cal r m s p h as e no is e (100 h z t o 100 kh z) o f th e l o in this co nf igura t io n is 0.09 . t h e r e f e r e n c e fr e q u e n c y i s fr o m a 1 6 m h z t c x o fr o m f o x ; th u s , a n r v a l u e o f 2 i s p r o g ra m m ed . t a k i n g i n t o a c c o un t th e h i gh p f d fr e q ue n c y a n d i t s e f f e ct o n t h e ba n d s e l e ct l o g i c , th e ba n d se l e ct c l oc k div i der is en ab le d . i n t h i s ca s e , a va lue o f 8 is ch o s e n . a ver y sim p l e sh u n t ind u c t o r and dc b l o c k i n g c a p a c i t o r com p l e t e t h e rf output s t ag e. spi -c ompa ti b l e ser i a l b u s adf4360-8 v vco v vco fox 801be-160 16mhz v vco cpgnd agnd dgnd l1 l2 rf out b rf out a cp 1nf 47pf 68nh 470 ? 68nh 470 ? 22nf 56nh 56nh 680pf 51 ? 100pf 100pf 1nf 1nf 10 f 4.7k ? 6.8k ? 15k ? r set c c le data clk ref in c n v tune dv dd av dd ce muxout 5 4 24 7 20 23 2 21 6 14 16 17 18 19 13 1 3 8 9 10 11 22 15 12 v vdd lock detect 04763- 027 fi g u r e 2 3 . fi x e d fr e q u e n c y l o
adf4360-8 rev. 0 | page 20 of 24 power-up af t e r p o w e r - u p , t h e p a r t n e e d s t h r e e wr i t es fo r n o r m al o p er a - ti o n . th e co rr ect seq u en ce i s t o th e r co un t e r la t c h , f o llo w ed b y th e con t r o l la t c h, a nd n co un ter la t c h. interfacing the ad f4360 f a mil y has a sim p le s p i? co m p a t i b le s e r i al in t e r - face f o r wr i t in g t o th e de vice . clk, d a t a , and le co n t r o l th e da ta tra n s f e r . w h en l e g o e s h i g h , th e 24 b i t s tha t ha v e been cl o c ke d i n to t h e a ppropr i a t e re g i ste r on e a c h r i s i ng e d g e of c l k a r e t r a n sfer r e d t o t h e a p p r o p r i a te la t c h. s e e f i gu r e 2 fo r t h e ti m i n g di a g ra m a n d t a b l e 5 f o r th e la t c h tr u t h t a b l e . the max i m u m a l lo wa ble s e r i a l clo c k r a te is 20 mh z. t h is m e an s tha t the maxim u m u p da t e ra te p o s s ib le is 833 kh z o r o n e up da t e e v er y 1.2 s. this is cer t a i nly m o r e t h a n ade q u a te fo r sys t em s t h a t ha v e typ i cal lo ck t i m e s in h u ndr e ds o f micr o- sec o n d s . aduc812 interface f i gur e 24 s h o w s th e in t e r f ace betw een t h e ad f 4360 fa mil y an d th e aduc812 m i cr oc o n v e r t er?. s i n c e t h e ad uc812 is bas e d o n a n 8051 co r e , this in t e r f ace can be us e d wi t h an y 8051-bas e d micr o c o n t r ol lers. th e micr oc o n v e r t er is s et u p fo r s p i mas t er m o de wi t h cph a = 0. t o ini t i a t e t h e op era t ion, t h e i / o p o r t dr i v in g le is b r o u g h t lo w . e a c h la t c h o f th e adf4360 fa mil y ne e d s a 2 4 - bit word, w h i c h i s a c c o m p l i s h e d by w r it i n g t h re e 8-b i t b y t e s f r o m t h e micr oc on ver t er t o t h e de v i ce . af t e r t h e t h ir d b y t e has b e en wr i t t e n, t h e le in p u t sh o u ld b e b r o u g h t hig h t o com p lete t h e t r an sfer . 04763-028 aduc812 adf4360-x sclk sdata le ce muxout (lock detect) sclock mosi i/o ports f i g u re 24. a d uc8 1 2 t o a d f4 3 60-x i n t e r f ace i/o p o r t lin e s o n the adu c 812 a r e als o us ed t o co n t r o l p o w e r - do wn ( c e i n p u t ) a nd dete c t lo ck ( m u x ou t c o nf igur e d as lo ck det e c t and p o l l e d b y t h e p o r t in p u t). w h en o p e r a t in g i n t h e des c r i b e d m o de, th e maxim u m scl o ck ra te of th e adu c 812 is 4 mh z. this m e an s t h a t t h e maxim u m ra te a t w h ich t h e o u t p u t f r eq uen c y ca n be c h an g e d is 166 kh z. adsp-2181 interface f i gur e 25 s h o w s th e in t e r f ace betw een t h e ad f 4360 fa mil y an d th e ads p -21xx dig i t a l sig n al p r o c es s o r . the ad f4360 fa mil y n e e d s a 24- b i t s e r i al w o r d fo r e a ch l a t c h wr i t e . the e a siest wa y t o acco m p lish t h is usin g t h e a d s p -21xx fa mi ly is t o us e t h e a u t o b u f f er e d t r an smi t m o de o f o p era t ion wi t h al t e r n a te f r a m - i n g . t h i s prov i d e s a m e ans f o r t r ans m itt i ng an e n t i re bl o c k of se ri al d a ta be f o r e a n in t e rr u p t i s g e n e ra t e d . 04763-029 adsp-21xx adf4360-x sclk sdata le ce muxout (lock detect) sclock mosi tfs i/o ports f i g u re 25. a d s p -2 1 x x to a d f4 3 60-x i n ter f a c e s et u p t h e w o r d len g t h fo r 8 b i t s a nd us e t h r e e m e m o r y lo ca - tio n s f o r eac h 24-b i t w o r d . t o p r ogra m eac h 24-b i t la t c h , s t o r e t h e 8- b i t b y t e s, ena b le t h e a u t o b u f f er e d mo de , a nd wr i t e t o t h e tra n s m i t r e gis t er o f th e d s p . t h i s la s t o p e r a t i o n i n i t ia t e s t h e a u t o b u f f er t r a n sfer . pcb desig n guidelines for chip sc ale packag e the le ads o n t h e chi p s c ale p a cka g e (c p - 24) a r e r e c t a n gu la r . the p r in te d cir c ui t b o a r d p a d for t h es e sh o u ld b e 0.1 mm lo n g e r th a n th e pa c k a g e lead len g th a n d 0. 05 m m w i d e r th a n t h e p a cka g e le ad w i d t h. th e le ad sh o u ld b e ce n t er e d on t h e p a d t o en s u r e t h a t t h e s o lder join t s i ze is maximize d . the b o t t o m o f t h e chi p s c ale p a cka g e has a ce n t ral t h er mal p a d . the t h er mal p a d o n t h e p r i n t e d cir c ui t b o a r d sh o u ld b e a t le ast as la rg e as t h is e x p o s e d p a d . o n t h e p r in t e d cir c ui t b o a r d , t h er e s h o u ld b e a cle a ra n c e o f a t le as t 0.25 mm b e tw e e n t h e t h er mal p a d an d t h e in ner e d ges o f t h e p a d p a t t er n to e n sur e t h a t sh o r t - in g is a v o i de d . ther mal v i as ma y b e us e d on t h e p r i n t e d cir c ui t b o a r d t h er mal p a d t o im p r o v e t h er mal p e r f o r ma nce o f t h e p a cka g e . i f vi as a r e used , th ey s h o u ld be in co r p o r a t e d i n t o th e th e r m a l pa d a t 1.2 mm pi t c h g r id . th e v i a diamet er s h o u ld b e b etw e e n 0.3 mm a nd 0.33 m m , and t h e v i a b a r r el sh o u ld b e pla t e d wi t h 1 o u nce o f co p p er t o p l ug th e via . the us er s h o u ld co nne c t t h e p r i n t e d cir c ui t t h er mal p a d t o a g nd . this is i n t e r n a l ly co nne c t e d t o a g nd .
adf4360-8 rev. 0 | page 21 of 24 outpu t ma tchi ng ther e a r e a n u m b er o f wa ys t o ma t c h t h e o u t p u t o f t h e ad f4360-8 f o r o p tim u m o p er a t io n; the m o s t b a sic is t o us e a 5 0 ? re s i stor to v vc o . a dc b y p a s s ca p a c i t o r o f 100 pf is c o n n e c t e d i n s e r i e s a s show n i n f i g u re 2 6 . b e c a u s e t h e re s i stor i s not f r e q u e nc y d e p e nd e n t , t h i s prov i d e s a go o d b r o a d b a n d ma t c h. th e o u t p u t p o w e r in t h e cir c ui t b e lo w t y p i cal l y g i v e s ?9 dbm o u t p u t p o w e r in to a 50 ? lo ad . l 100pf 04763-031 rf out v vco 50 ? f i g u re 27. o p t i m u m a d f 4 3 60- 8 o u t p ut st ag e 100pf 04763-030 rf out v vco 50 ? 51 ? t h e re c o m m e n d e d v a lu e of t h i s i n d u c t or ch an ge s w i t h t h e v c o ce n t e r f r eq uen c y . a gra p h o f th e o p ti m u m in d u ct o r v a l u e v e r s us f r e q u e nc y i s sh ow n i n f i g u re 2 8 . centre frequency (mhz) inductance (nh) 300 250 150 200 100 0 50 0 100 200 300 5000 400 04763-032 f i gure 26. si mpl e a d f43 6 0 -8 o u tput s t age a bet t er s o l u tio n is t o us e a sh u n t ind u c t o r (ac t in g as an rf cho k e) to v vc o . this g i v e s a b e t ter ma t c h an d , t h er efo r e , m o r e output p o we r . e x p e r i me n t s h a ve sho w n t h a t t h e c i rc u i t s h ow n i n fi g u re 2 7 p r o v ides a n exc e l l en t ma t c h t o 50 ? o v er t h e o p era t i n g ra n g e o f th e ad f4360-8. this g i v e s a p p r o x ima t e l y 0 dbm o u t p u t p o w e r acr o s s th e sp ecif ic f r eq uen c y ra n g e o f th e ad f 4360-8 usin g the r e co mmen d e d sh un t in d u c t o r , f o l l o w ed b y a 100 pf dc b l o c king c a pa ci t o r . f i g u re 28. o p t i m u m a d f 4 3 60- 8 s h un t induc t o r b o t h c o m p l e me n t ar y arch i t e c tu re s c a n b e e x am i n e d u s i n g t h e e v al -ad f 4360-8eb1 eval u a tio n bo a r d . i f th e us er do es n o t n e e d t h e dif f er en tial o u t p u t s a v a i la b l e on t h e ad f4360-8, th e use r s h o u ld ei th e r t e rm i n a t e th e un used o u t p u t o r co m b in e b o t h o u t p u t s usin g a b a l u n. a l ter na t i vely , inste a d o f t h e lc bal u n, bo th o u t p u t s ma y be com b in e d usin g a 180 ra t-rac e co u p ler .
adf4360-8 rev. 0 | page 22 of 24 outline dimensions 1 24 6 7 13 19 18 12 2.25 2.10 sq 1.95 0.60 max 0.50 0.40 0.30 0.30 0.23 0.18 2.50 ref 0.50 bsc 12 max 0.80 max 0.65 typ 0.05 max 0.02 nom 1.00 0.85 0.80 seating plane pin 1 indica t o r to p view 3.75 bsc sq 4.00 bsc sq pin 1 indicator 0.60 max coplanarity 0.08 0.20 ref 0.25 min exposed pad (bottom view) compliant t o jedec st and ards mo-220-v ggd-2 f i gure 29. 2 4 -l ead l e ad f r a m e ch ip s c a l e p a ck ag e [lfcs p ] 4 mm 4 m m b o d y (cp - 2 4 -1) di me nsio ns sho w n i n mi ll im e t e r s ordering guide model temperature r a nge frequency r a nge package option adf4360-8bcp ?40c to +85c 65 mhz to 400 mhz cp-24-1 adf4360-8bcprl ?40c to +85c 65 mhz to 400 mhz cp-24-1 adf4360-8bcprl7 ?40c to +85c 65 mhz to 400 mhz cp-24-1 eval-adf4360- 8 e b 1 e v a l u a t i o n boar d
adf4360-8 rev. 0 | page 23 of 24 notes
adf4360-8 rev. 0 | page 24 of 24 notes purch a se of li c e n s e d i 2 c com p on en t s o f an a l og d e vi ces or on e of i t s subli c en s e d as soci a t ed c o m p a n i e s con v eys a li cen s e for t h e purch a ser un der t h e ph i li p s i 2 c p a te nt rights to us e the s e co mpo n e nts in an i 2 c sy st em , provi d e d t h a t t h e syst em c o n f orm s t o t h e i 2 c stand a rd speci f ication as d e f i ned by phil ips . ? 2004 analo g de vices, inc. all rights reserve d . tra d em arks and registered tra d ema r ks are the prop erty of their respective owners . d04763C0C 10/04(0)

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